Computers and other data processing equipment require memory devices to store data to be processed and a processor to process the data. To process the data, the data are moved from the memory devices to the processor, where the data are processed. Then, the results of the processing are moved to the memory devices. Thus, memory read operations are performed to move data from the memory devices to the processor and memory write operations are performed to move results of the processing from the processor to the memory devices. Memory read operations and memory write operations may be performed for other purposes, as well. For example, memory write operations may be used to store data in the memory devices prior to processing. Likewise, for example, memory read operations may be used to read the results of the previous processing operations from the memory devices after those processing operations have occurred. Memory read operations are also used to fetch instructions.
As faster computers and other data processing equipment are developed, concurrency continues to increase, for example, through multiprocessing and multithreading. The concurrency can lead to multiple outstanding memory read and write operations. As concurrency increases, the amount of information that can be communicated with memory devices per unit time, which may be referred to as memory bandwidth, needs to increase.
Each of the memory devices can hold only a certain amount of data. Since it is often necessary to process very large amounts of data, several memory devices are often grouped together to store the data. The memory devices are coupled to the processor by a bus. The processor and the memory devices are coupled to the bus at specific locations along the bus. Thus, one memory device may be closer to or farther from the processor than another memory device.
In the past, data were communicated over the bus relatively slowly, and the data were thought of as being present on the bus as a whole for a given period of time. Actually, as with any signal, the data can only propagate along the bus at a finite speed, limited by such factors as the speed of light and the dielectric constant associated with the bus. Thus, when data are communicated at sufficiently high rates, the data will not necessarily be present on the bus as whole at a given time, but will propagate as pulses along the bus in a manner reminiscent of waves propagating along the surface of a body of water.
Such pulses propagate in both directions along the bus. Moreover, if an end of the bus is not terminated with an impedance to match the characteristic impedance of the bus, pulses reaching that end of the bus will be reflected back along the bus in the opposite direction. For this reason, it is preferable to provide a termination for at least one end of the bus. While pulses may reflect from the unterminated end of the bus, the reflected pulses will eventually disappear from the bus when they reach the bus termination.
In the past, to avoid interference from multiple pulses and their reflections, memory bus operations were scheduled to occur only after the pulses and their reflections have had time to propagate along the bus to the bus termination. While the actual time for pulses and reflections to clear from the bus may vary depending on the location of a memory device along the bus, historically, a standardized delay in scheduling has been used, treating all memory devices as requiring the same amount of time for the bus to clear. Consequently, such scheduling has yielded relatively low channel efficiency. Low channel efficiency refers to the relatively low fraction of time that the bus is actually carrying data and the relatively high fraction of time during which further data cannot be carried over the bus while the pulses and their reflections are still present on the bus.
Thus, a technique is needed to increase the channel efficiency to provide more efficient utilization of the bus and a higher rate of data processing.